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Rework, MPWs and “right first time”
While electronic circuits often do not perform to specification first time, with ASICs this is a particular issue because it is not usually possible to make a small adjustment to correct a deficiency, unlike changing a component on a PCB or making a track cut and wire link. Also, the costs of re-working an ASIC are considerably higher than having a PCB remade.
However, Key Design has a first time success rate of over 90% with ASIC designs. Even if an ASIC rework is required, the 700 series bipolar array rework costs are low because there is only a single metallisation mask to change. With full custom CMOS, the initial NRE (non-recurring engineering charge) and rework costs are usually kept low by using a multi-project wafer (MPW) for the prototype chips.
ASIC Performance
An ASIC can be used to reduce cost, size, power consumption and/or improve performance. In some cases the cost savings come from the reduced assembly cost, rather than reduced component cost, particularly in lower volume products where component placement costs can be significant. For low volume products (maybe 10,000 units per annum or less), the Zetex arrays can be particularly attractive at reducing assembly costs.
Specifications can be achieved with ASICs which would be impossible without an ASIC. This is because functional blocks can be designed to only what is required and no more. For example, and opamp which doesn’t need to drive off chip can have a reduced output stage current, or no final output stage at all, thus reducing current dramatically. An opamp with 58MHz GBW (gain bandwidth product) drawing only 16µA from a nominal 3.3V supply has been designed in 0.8µm CMOS and specified for operation down to 2.8V. Similarly, a comparator drawing only 2.5µA with 200ns delay. DACs (digital to analogue converters [digital to analog converters]) drawing less than 5µA have also been designed. These can be non-linear if required.
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