Level shifting CMOS comparator
Analysis
Transimpedance amplifier
Bias generator
Click on the image for a larger view of the schematic.
This simple cross-coupled clamped comparator was designed as part of a larger custom chip for a low power battery operation. The process was 0.8µm CMOS. With a 1µA bias current to IB it takes only 2µA to 2.5µA depending on the output state. Nominal operating voltages were 2.8V for the regulated supply (derived on chip) and 3.5V for the unregulated. Switch speed is around 550ns with 10mV overdrive. The output was buffered by a specially designed tri-state Schmitt trigger before being processed by digital logic.
The cross-coupled clamped comparator is covered by many IC design reference books, such as "VLSI Design Techniques for Analog and Digital Circuits" by Geiger, Allen & Strader ISBN 0-07-023253-9.
This simple cross-coupled clamped comparator was designed as part of a larger custom chip for a low power battery operation. The process was 0.8µm CMOS. With a 1µA bias current to IB it takes only 2µA to 2.5µA depending on the output state. Nominal operating voltages were 2.8V for the regulated supply (derived on chip) and 3.5V for the unregulated. Switch speed is around 550ns with 10mV overdrive. The output was buffered by a specially designed tri-state Schmitt trigger before being processed by digital logic.
The cross-coupled clamped comparator is covered by many IC design reference books, such as "VLSI Design Techniques for Analog and Digital Circuits" by Geiger, Allen & Strader ISBN 0-07-023253-9.
CMOS comparator
